When semiconductor components are made on SOI-wafers impurity behaviour is different to bulk silicon wafers. In bulk silicon wafers there are several gettering techniques available which are effective to remove impurities, especially certain metallic elements, from the active semiconductor area. In SOI wafers, where the structure of the wafer normally consists of a substrate silicon wafer, or a handle silicon wafer, buried oxide and of a silicon layer where semiconductor devices are made, normally used gettering methods are not usually available. The lacking gettering efficiency is limiting the usability of wafers in critical semiconductor applications where, for example, the integrity of gate oxide, and hence the high voltage reliability, is critical. The lack of efficient gettering methods is especially pronounced is such devices, where relatively thick active layers in SOI are used, typically more that few micrometers thick. There is requirement of thick active layers especially in sensor components. To minimize the cost of the sensor component, more often the sensing part, sensing motion are change in the motion, pressure of some other physical phenomenon, and the semiconductor part, processing the information from sensor part, are integrated on the same silicon chip. These sensor components, both the sensing part and semiconductor part, are often used in critical environment or application, as an example in automotives or aviation equipment, where human lives depend on the sensor reliability. This reliability requirement is also very long term, typically well over ten years. It is therefore of paramount importance that the semiconductor part performance is not degraded by impurities, the gettering has to be effective.
It is known that about SOI wafers, having thin active layer, typically from few tens of nanometres to hundreds of nanometres, several techniques are published as such. These SOI wafers are made for example with SmartCut® or similar techniques like plasma immersion process. To improve gettering a thin polysilicon layer between a bond interface and active layer can be used, for example. However, in practise these techniques produce too thin layers suitable for sensor manufacturing. Many of the sensors sense external force, and because of the noise limitations of the amplifying semiconductor part, to get enough sensitivity, according to Newton's law a minimum mass is required. Typically when the sensing element lateral dimensions have to be minimized because of cost reasons, practical active layer thickness is in the order of 10 micrometers or even thicker. In pressure sensors using as a sensing membrane SOI active layer, the durability of the sensor sets minimum practical layer thickness limit. Furthermore, SOI manufacturing techniques based on implantation of ions have practical limitations due to manufacturing cost reasons in ion penetration depth, thus polysilicon layer thickness is in practice limited.
It is possible to use SOI wafers with thin active layers in these applications only if the active layer thickness is increased with an epi-process. However, the cost of the wafers is increasing and the total cost of sensor manufacturing process is too high.
Alternative methods using wafer bonding and back lapping and polishing do not produce enough uniformity in active layer, both within wafer and from wafer to wafer. The requirement commonly is the active layer uniformity of +/−0.5 μm or better in modern component designs.
Known most advantageous SOI wafers for sensor applications with thick active layers are made by bonding wafers together, and then thinning top wafer to a de sired thickness by precision grinding, followed by optional etching and polishing.
In such a way active layer thickness uniformity and overall quality can be produced to meet demanding requirements. Furthermore, what is important and advantageous for the bonding-precision grinding-polishing technique is that when the SOI wafer has buried oxide or other insulating layer, the position of the bond interface and the thickness of the insulating layer can be selected freely.
The patent publication U.S. Pat. No. 6,890,838 discloses a gettering technique for wafers made using a controlled cleaving process for integrated circuits. Therein, the gettering layer is made by implanting using beam line or immersion ion implantation. According to the patent document, a film of material such as polysilicon by way of chemical vapour deposition can be made. A controlled cleaving process can be used to form the wafer.
According to the patent publication U.S. Pat. No. 6,083,324 a gettering layer in a silicon-on-insulator can be formed by implanting gas-forming particles or precipitate-forming particles beneath the active region of the silicon layer and thermally treating the gas forming ions to produce micro bubbles or precipitates within the silicon layer. The micro bubbles and/or precipitates are meant to create trapping sites for mobile impurity species, thus gettering them. The document indicates also that a polysilicon layer is formed on a donor silicon wafer for separating a thin layer of silicon from the donor wafer. According to the patent publication the thin layer of silicon is bonded to a backing wafer. The polysilicon layer can be used to provide a gettering layer between an active silicon layer and the backing wafer.
In a known technique, two layers of separate crystalline and poly-silicon layers are used so for facilitating the implantation of hydrogen through the poly-crystalline silicon to the separate crystalline layer. In known techniques, the thickness of the poly-silicon limits the penetration of the hydrogen implantation into the active layer and thus limits the thickness of the separate crystalline silicon. Although the implantation energy as such can be increased, such increasing becomes impractical at certain energies according to the estimates of a skilled man in the art. In practice, this means that the poly silicon layer cannot be of arbitrary thickness, rather than below a certain layer thickness.
There are known gettering techniques as such for wafers having thick active layer. One possibility is to etch deep trenches for example with RIE technique and diffuse through the sidewalls suitable element, for example phosphorus or boron, U.S. Pat. Nos. 6,830,986 and 5,646,053, for gettering purposes and fill the trenches, and planarize the wafer after that. Although this method is effective it is very expensive, and it requires quite many process steps. It is also possible to diffuse suitable element on the surface of the wafer and to use lateral gettering technique, but again this requires additional process steps and consumes surface area. Furthermore, the gettering efficiency is decreasing with increasing distance from the gettering site.